`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:25:04 10/21/2012 
// Design Name: 
// Module Name:    Paddle_Unit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Paddle_Unit(clk_i,reset_sync,up_sync,down_sync,paddle_y);
	input clk_i, reset_sync, up_sync, down_sync;
	output [9:0] paddle_y;
	localparam [9:0] PADDLE_INI = 130;
	localparam [9:0] MAX_Y = 400;
	localparam [2:0] PADDLE_V = 5;
	localparam [9:0] PADDLELONG = 82;
	reg [9:0] paddle_y, bar_y_b;
	initial begin
		paddle_y = PADDLE_INI;
	end
   always@(posedge clk_i)
      if (reset_sync) 
		begin
         paddle_y <= PADDLE_INI;
      end
      else
			begin
				bar_y_b <= paddle_y + PADDLELONG;
					if ( down_sync && (bar_y_b < (MAX_Y-1-PADDLE_V))) begin
							paddle_y <= paddle_y + PADDLE_V; 
					end
					else if ( up_sync && (paddle_y > PADDLE_V)) begin
							paddle_y <= paddle_y - PADDLE_V; 
					end
			end
        
endmodule
